昔のArty用VivadoプロジェクトデータをVivado2017.2でビルドすると、bitgenで次のエラーが発生しました。
[DRC NSTD-1] Unspecified I/O Standard: 4 out of 66 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_4bits_tri_o[3:0].
[DRC UCIO-1] Unconstrained Logical Port: 4 out of 66 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_4bits_tri_o[3:0].
LEDのピンでエラーが出ています。プロジェクトをVivado2020.1で作りなおすと、このエラーは発生しません。そこで、2つのプロジェクトの結果を比較すると、そもそもピンアサインが異なっていました。
まず、Vivado2017.2の結果。
| R10 | led_4bits_tri_o[0] | High Range | IO_25_14 | OUTPUT | LVCMOS18* | Vivado2020.1の結果。
| H5 | led_4bits_tri_io[0] | High Range | IO_L24N_T3_35 | BIDIR | LVCMOS33 |エラーの原因
H5が正しいピンアサインなので、Vivado2017.2の結果はそもそもピンアサインが間違っています。また、電圧の設定もLVCMOS33ではなく、LVCMOS18になっています。
以下のような制約条件を追加することで、Vivado2017.2でも問題なくビルドできました。
set_property PACKAGE_PIN H5 [get_ports led_4bits_tri_o[0]]
set_property PACKAGE_PIN J5 [get_ports led_4bits_tri_o[1]]
set_property PACKAGE_PIN T9 [get_ports led_4bits_tri_o[2]]
set_property PACKAGE_PIN T10 [get_ports led_4bits_tri_o[3]]
set_property IOSTANDARD LVCMOS33 [get_ports led_4bits_tri_o[0]]
set_property IOSTANDARD LVCMOS33 [get_ports led_4bits_tri_o[1]]
set_property IOSTANDARD LVCMOS33 [get_ports led_4bits_tri_o[2]]
set_property IOSTANDARD LVCMOS33 [get_ports led_4bits_tri_o[3]]何故BIDIR
Vivado2020.1でVivadoで自動生成したwrapperは、LEDのI/Oが双方向になっています。しかもIOバッファがわざわざインスタンス化されています。LEDを普通に出力ポートとして処理していない理由が謎です。動作に問題はありませんが、少し気になります。
IOBUF led_4bits_tri_iobuf_0
(.I(led_4bits_tri_o_0),
.IO(led_4bits_tri_io[0]),
.O(led_4bits_tri_i_0),
.T(led_4bits_tri_t_0));
IOBUF led_4bits_tri_iobuf_1
(.I(led_4bits_tri_o_1),
.IO(led_4bits_tri_io[1]),
.O(led_4bits_tri_i_1),
.T(led_4bits_tri_t_1));
IOBUF led_4bits_tri_iobuf_2
(.I(led_4bits_tri_o_2),
.IO(led_4bits_tri_io[2]),
.O(led_4bits_tri_i_2),
.T(led_4bits_tri_t_2));
IOBUF led_4bits_tri_iobuf_3
(.I(led_4bits_tri_o_3),
.IO(led_4bits_tri_io[3]),
.O(led_4bits_tri_i_3),
.T(led_4bits_tri_t_3));