Link Layer – Software Driver

Internet Protocol Suite

The software driver implements low-level API to handle Ethernet Frame transfer between the Link Layer and the Internet Layer.

void ether_write_frame(int flen,unsigned char *fbuf);

• Description
  • The function copies the number of bytes specified by flen from fbuf to Local Memory in the FPGA, and send it as an Ethernet Frame.
• Return Value
  • None

int ether_read_frame(unsigned char *fbuf);

• Description
  • The function stores received Ethernet Frame from Local Memory in the FPGA to fbuf.
• Return Value
  • The function returns the number of bytes of received Ethernet Frame on success.

An Ethernet Frame is transmitted in the following way.

1. Copies Frame data from CPU main memory to FPGA Local Memory
2. Set Mode Register TXEN bit of MAC Core to 1
3. Set Local Memory address which the data stored in to TXPNT of Tx Buffer Descriptor register in MAC Core.
4. Set Tx Buffer Descriptor RD bit of MAC Core to 1.
5. Wait for transmit complete interrupt.
6. Clear the interrupt.

Ethernet Frame Transmit Flow Chart

Frame CRC will be calculated and added to the end of the Frame. After Tx Buffer Descriptor is enabled, Ethernet MAC Core reads data from Local Memory then send it to PHY as an Ethernet Frame.

 void ether_write_frame(int flen,unsigned char *fbuf) {
     int i, flush;
     struct st_txdesc_l txl;
     unsigned int a;
     // Tx Buffer Descriptor configuration
     txl.LONG = 0;
     txl.IRQ = 1; // Interrupt Request Enable
     txl.PAD = 1; // PAD Enable
     txl.CRC = 1; // CRC Enable
     txl.WR = 1; // Wrap 
     // Store Frame to Local Memory in FPGA
     a = ETHER_BUF_TX_BASE;
     for (i=0; i< flen;i++) {
         if (((a+i) % 4) == 3) flush = 1;
         else flush = 0;
         if (i == (flen -1)) flush = 1; // final data
         ether_write_byte(a+i, fbuf[i], flush);
     }

     // set Tx Buffer Descriptor ready bit 
     txl.RD = 1;
     (*(volatile unsigned int *)(ETHER_BD_BASE)) = txl.LONG;
 }

An Ethernet Frame is received in the following way.

1. Set Mode Register RXEN bit of MAC Core to 1
2. Set Local Memory address, which specifies the data to be received to RXPNT of Rx Buffer Descriptor in MAC Core.
3. Set Rx Buffer Descriptor E bit of MAC Core to 1.
4. Wait for reception complete interrupt.
5. Clear the interrupt.
6. Copies Frame data from FPGA Local Memory to CPU main memory.

Ethernet Frame Reception Flow Chart

The Frame data from PHY is transferred from Ethernet MAC Core to Local Memory according to the configuration of Rx Buffer Descriptor register. CRC in the Frame is removed and not stored in Local Memory.

 int ether_read_frame(unsigned char *fbuf) {
     int i,j,p, size,s;
     unsigned int x;
     struct st_rxdesc_l rxl;

     // Read byte data from FPGA to CPU
     rxl.LONG = (*(volatile unsigned int *)(ETHER_BD_RX_BASE+ether_cur_rx_bd*8));
     size = rxl.LEN; // byte size
     p =0;
     s = size /4;
     if ((size %4 ) != 0) s++;
     for (i = 0; i< s; i++) {
     x =(*(volatile unsigned int *)(ETHER_BUF_RX_BASE+ether_cur_rx_bd*ETHER_BUFFER_SIZE+i*4));
     for (j=0;j <4; j++) {
         fbuf[p] = (x > (3-j)*8)&0xff; // copy each byte
         p++;
     }
     }
     // set Rx Buffer Descriptor empty bit
     rxl.LEN = 0;
     rxl.E = 1;

     (*(volatile unsigned int *)(ETHER_BD_RX_BASE+ether_cur_rx_bd*8)) = rxl.LONG;

     if (ether_cur_rx_bd == (ETHER_MAX_RX_BD-1))
         ether_cur_rx_bd = 0;
     else
         ether_cur_rx_bd++;

     return size;
 }