USB Host

USB HostSlave IP Core


USB HostSlave IP Core, is an open source IP core freely available from OpenCores*1. This core is used for the FPGA system implementation.

USB Core Stand-Alone Test

First, run the IP core under the following stand-alone environment:

  • OS: Windows XP Cygwin
  • Simulator: ModelSim

Download the archive data from the web site, then extract the data in a work directory.

The following directories are extracted.

Put the simulation script for ModelSim under the bench directory.

The bench directory contains simple test scenario (testCase0.v) . The test scenario is confirmed under Quartus, but some errors occur in ModelSim environment while compile phase .To correct the errors, the following few modifications are added to 2 files in bench directory.
(testCase0.v )

(sepHostSlaveTestHarness.v )

Run the ModelSim with the test scenario(./ testCase0.v). Simple tests(USB host and device connection, and basic data transfer) are executed.

(Execution Log)

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