USBシステム: USBホストCoreについて

OpenCores

FPGAに実装するUSBホストCoreは、OpenCores*1で配布されているオープンソースのUSB IP Core(USB 1.1 Host and Function IP core)を利用しました。

Coreの動作確認

次の環境で、Core自体の単体動作確認を行いました。

OS: Windows XP Cygwin
シミュレータ: ModelSim

Webサイトからダウンロードしたデータを適当なディレクトリで展開します。

$tar xvzf usbhostslave_latest.tar.gz

展開すると次のディレクトリが生成されます。

trunk
 RTL
 bench
 doc
 mode
 sim
 syn
 usbDevice

ModelSimでシミュレーションを実行するために、以下のスクリプトをbenchディレクトリに作成します。
(bench/run.sh)

#!/bin/csh -f
# modelsim simulation script
set RTL_DIR = "../RTL"
set MODEL_DIR = "../model"
set XILINX_DIR = "C:\Xilinx\10.1\ISE\verilog\src"
set MODELSIM = "C:\Modeltech_xe_starter\xilinx\verilog"

if (!(-d ./work)) then
 vlib ./work
endif
if ($#argv) then
 set sim_file = $argv[1]
else
 echo "usage : run.sh [verlog file]"
 exit(1)
endif

vlog \
 +notimingchecks \
 -y . \
 -y ${RTL_DIR} \
 -y ${RTL_DIR}/buffers \
 -y ${RTL_DIR}/busInterface \
 -y ${RTL_DIR}/hostController \
 -y ${RTL_DIR}/hostSlaveMux \
 -y ${RTL_DIR}/include \
 -y ${RTL_DIR}/serialInterfaceEngine \
 -y ${RTL_DIR}/slaveController \
 -y ${RTL_DIR}/wrapper \
 -y ${MODEL_DIR} \
 -y ${XILINX_DIR} \
 -y ${XILINX_DIR}/unisims \
 +incdir+${RTL_DIR}/+ \
 +incdir+${RTL_DIR}/include+ \
 +libext+.v+ \
 $sim_file

vsim -keepstdout testCase0 testHarness <<
run -all
EOF

benchディレクトリにはQuartusで動作確認が行われているテストベンチ(testCase0.v)があります。そのまま実行するとModelSimではエラーが発生する為、testCase0.vとsepHostSlaveTestHarness.vに次の修正を加えます。
(testCase0.v )

// ---------------------------------- testcase0.v ----------------------------
`include "timescale.v"
`include "usbHostSlave_h.v"
`include "usbHostControl_h.v"
`include "usbHostSlaveTB_defines.v"
`include "wishBoneBus_h.v" // added 
`include "usbSlaveControl_h.v" // added
`include "sepHostSlaveTestHarness.v" // added

(sepHostSlaveTestHarness.v )

module testHarness( );

// -----------------------------------
// Local Wires
// -----------------------------------
wire USBDPlusPullup; // added
wire USBDMinusPullup; // added
reg clk;
reg rst;
reg usbClk;
wire [8:0] adr;

benchディレクトリでテストベンチを実行します(./run.sh testCase0.v)。USBホストとデバイスの接続テストと、シンプルなデータ転送が実行されます。

(実行ログ)

Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005
-- Compiling module testHarness
-- Compiling module testCase0
-- Scanning library directory '.'
-- Scanning library directory '../RTL'
-- Scanning library directory '../RTL/buffers'
-- Scanning library directory '../RTL/busInterface'
-- Scanning library directory '../RTL/hostController'
-- Scanning library directory '../RTL/hostSlaveMux'
-- Scanning library directory '../RTL/include'
-- Scanning library directory '../RTL/serialInterfaceEngine'
-- Scanning library directory '../RTL/slaveController'
-- Scanning library directory '../RTL/wrapper'
-- Compiling module usbHost
-- Compiling module usbSlave
-- Scanning library directory '../model'
-- Compiling module wb_master_model
-- Scanning library directory 'C:\Xilinx\10.1\ISE\verilog\src'
-- Scanning library directory 'C:\Xilinx\10.1\ISE\verilog\src/unisims'
-- Scanning library directory '.'
 :
 :
 :
Top level modules:
 testHarness
 testCase0
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 6.0d
 :
 :
 :
# vsim -keepstdout testCase0 testHarness 
# Loading work.testCase0
# Loading work.testHarness
# Loading work.usbHost
# Loading work.usbHostControl
# Loading work.USBHostControlBI
# Loading work.hostcontroller
# Loading work.SOFController
# Loading work.SOFTransmit
# Loading work.sendPacketArbiter
# Loading work.sendPacketCheckPreamble
# Loading work.sendPacket
# Loading work.directControl
# Loading work.HCTxPortArbiter
# Loading work.getPacket
# Loading work.rxStatusMonitor
 :
 :
 :

run -all
# 
# 
# Host Version number = 0x20
# 
# Slave Version number = 0x20
# 
# Testing host register read/write --- PASSED
# Testing slave register read/write --- PASSED
# Testing register reset --- PASSED
# Configure host and slave mode. Connect full speed --- PASSED
# Cancel interrupts --- PASSED
# Disconnect --- PASSED
# Connect full speed --- PASSED
# Host forcing reset --- PASSED
# Connect full speed --- PASSED
# Trans test: Device address = 0x00, 2 byte SETUP transaction to Endpoint 0. Checking receive data --- PASSED
# Trans test: Device address = 0x5a, 20 byte OUT DATA0 transaction to Endpoint 1. Checking receive data --- PASSED
# Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2. Checking receive data --- PASSED
# Finished all tests
# Break at testCase0.v line 251
# Stopped at testCase0.v line 251
# < EOF>

*1 http://www.opencores.org/

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